Charla: On-Chip Interconnects in Heterogeneous MPSoC

Dr. Sören Sonntag (Intel) - 24 de Noviembre, 12:30h - Salón de Grados

HORARIO: 24 de Noviembre, 12:30h

LUGAR: Salón de Grados

TÍTULO: On-Chip Interconnects in Heterogeneous MPSoC

PONENTE: Sören Sonntag is responsible for the overall platform architecture including baseband, power management and transceiver components. He formerly worked as System-on-Chip lead architect for a 1 Gb/s LTE baseband SoC with overall responsibility of the hardware architecture. Sören received both a diploma degree and a Ph.D. degree in electrical engineering and information technology from Chemnitz University of Technology, Germany. He works on on-chip and off-chip interconnect solutions for multiprocessor platforms and has been co-organizer of multiple international workshops such as INA-OCMC, MES and AISTECS.

RESUMEN: On-chip interconnects in Multiprocessor System-on-Chip (MPSoC) are communication backbones that connect major parts of the system. Many challenges arise from tight performance, area and power constraints that are typically not discussed in academic work. In this talk a 5G mobile baseband SoC is used as an example to show real-life challenges and solutions for multi-Gb/s Networks-on-Chip. Critical architecture trade-offs are highlighted and additional requirements such as trace&debug capabilities and security aspects are addressed in this talk.

IDIOMA: inglés