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| Ambos lados, revisión anterior Revisión previa Próxima revisión | Revisión previa | ||
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computer_arquitecture [07/07/2008 12:13] raul |
computer_arquitecture [11/12/2017 13:15] (actual) |
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| Línea 2: | Línea 2: | ||
| - | **People** | + | ===== People ===== |
| * Manuel E. Acacio | * Manuel E. Acacio | ||
| Línea 12: | Línea 13: | ||
| * Francisco J. Villa | * Francisco J. Villa | ||
| - | **Ongoing Research** | + | ===== Ongoing Research ===== |
| * Low-power Designs | * Low-power Designs | ||
| Línea 20: | Línea 22: | ||
| * Fault tolerant coherence protocols | * Fault tolerant coherence protocols | ||
| - | **Summary of Activities** | + | ===== Summary of Activities ===== |
| In order to improve processor performance, we have proposed a technique to improve the performance of superscalar processors, reducing branch penalty by means of a strategy called Dual Path Instruction Processing (DPIP). We have also proposed a technique, referred to as Selective Throttling, to reduce energy consumption for those instructions that have been erroneously speculated. In the field of the input/output subsystem, we have developed a new filesystem, called DualFS, that writes data and metadata separately. In order to improve performance even more, we have added data prefetching and dynamic metadata reordering mechanisms. We have evaluated the new filesystem, comparing it with other filesystems with similar characteristics. the results achieved by DualFS are really spectaclar. Finally, we are also researching in the Symmetric Multiprocessors area. Starting from a new directory architecture designed by us, we have proposed new solutions to reduce the long latencies associated with L2 cache misses: 1) including a first-level directory inside the processor chip; 2) using a predictor in case of 3-hop misses; and 3) using a owner predictor when a shared cache line has to be invalidated. Additionally, we have designed a new cache coherence protocol to support the above mentioned mechanisms and eliminate the new race conditions. | In order to improve processor performance, we have proposed a technique to improve the performance of superscalar processors, reducing branch penalty by means of a strategy called Dual Path Instruction Processing (DPIP). We have also proposed a technique, referred to as Selective Throttling, to reduce energy consumption for those instructions that have been erroneously speculated. In the field of the input/output subsystem, we have developed a new filesystem, called DualFS, that writes data and metadata separately. In order to improve performance even more, we have added data prefetching and dynamic metadata reordering mechanisms. We have evaluated the new filesystem, comparing it with other filesystems with similar characteristics. the results achieved by DualFS are really spectaclar. Finally, we are also researching in the Symmetric Multiprocessors area. Starting from a new directory architecture designed by us, we have proposed new solutions to reduce the long latencies associated with L2 cache misses: 1) including a first-level directory inside the processor chip; 2) using a predictor in case of 3-hop misses; and 3) using a owner predictor when a shared cache line has to be invalidated. Additionally, we have designed a new cache coherence protocol to support the above mentioned mechanisms and eliminate the new race conditions. | ||